In modern computer systems, direct memory access (DMA) controllers are used to transfer data from a source location in, e.g., a memory system to a destination location within the computer system. Typically, the DMA controller sequences through read and write cycles to read data from the source location and write the data to the desired destination location. In this manner, the data transfer operation is off loaded from, e.g., a CPU to free the processing power of the CPU for the performance of other processing functions. The DMA controller utilizes memory addresses specified by the CPU to locate the source and destination locations for the data transfer.
In memory systems, an address space is used to uniquely define each data storage location available within the system. For example, an n-bit address will uniquely identify 2.sup.n locations with each unique value of the n-bit address being used to identify one of the 2.sup.n locations. Each address is aligned relative to the other addresses of the address space to define a predetermined amount of data at any one storage location, e.g., a byte (eight bits). In a byte aligned system, each address uniquely identifies a location storing one byte of data.
For efficiency of operation, word or longword aligned addresses are often used so that each data fetch or store from or to memory transfers two bytes (word) or four bytes (longword) at one time. In a longword aligned memory, each unique n-bit address value would still identify the beginning of a byte of data, however, the two lowest order bits &lt;1:0&gt; of each address are always set to 0:0 when accessing memory to align addressable locations at longword boundaries. The lowest order two bits &lt;1:0&gt; can be used to specify an offset within a longword to uniquely identify each one of the four bytes in the accessed longword, as may be required, during processing by a CPU. In the general case, the lowest m bits of an address are set to zero wherein m equals the number of bits required to offset memory location boundaries by the number of bytes, n, to be accessed in a single memory cycle. Of course, the m lowest bits can be used to locate a specific byte within the n byte block specified by an n byte aligned address.
In various DMA applications, a device, such as a CPU, will specify initial or base source and destination addresses for a block of data and a count number to indicate to the DMA controller the total number of bytes in the block to be transferred. The DMA controller will then proceed to transfer longwords, beginning at the initial source address to the initial destination address, while decrementing the count and incrementing each of the initial source and destination addresses to the next longword boundary with each longword transfer until the count equals zero to indicate that all of the bytes of the block have been transferred.
However, the DMA controller may be reading and writing the data from and to a longword aligned memory device such as a DRAM while one or both of the initial source and destination addresses specified by a CPU desiring a data block transfer, are not aligned at longword boundaries. Thus, known DMA controllers have been designed to shift bytes within data lines of a bus to align reads and writes to and from the DRAM at appropriate allowed data boundaries. As should be understood, the DMA controller operates most efficiently when it can shift and transfer multiple bytes of, e.g., a longword in parallel. The known DMA controllers must often use extra clock cycles to align bytes to proper memory boundaries or extra write cycles to do partial writes within aligned memory locations throughout a data transfer operation.
In addition, during reads and writes of data there are typically error conditions, exceptions and special character handling checks that must be performed relative to the data to guarantee the integrity of the data being transferred and to assure proper handling of certain bytes of the data, as may be required within the particular computer system where the data transfer occurs. It is generally advantageous to design the DMA controller to perform the various checks on the data while moving the data. In this manner, both the data transfer and data checking operations are off loaded from the CPU.
While known DMA controllers have been designed to perform certain exception handling and special character detection operations during a data transfer, these controllers perform the data check and transfer operations serially. In other words, the DMA controller will first read data from the source location, then perform data checking and then write the data to the desired destination location. The serial nature of the known DMA controller operation results in relatively low speed performance, which degenerates the advantages gained from the CPU off load.